This invention relates generally to insulated gate field effect transistors (IGFET) and metal oxide silicon transistors (MOSFET), and more particularly the invention relates to such transistors having a floating gate for use in electrically erasable, programmable read only memory (EEPROM) cells and flash EEPROM cells.
The MOSFET transistor has source and drain regions separated by a channel region with the conduction of the channel region controlled by voltage biasing an overlying control gate. The flash EEPROM device has the structure of a MOSFET but includes an electrically isolated gate, or floating gate, between the control gate and the channel region for storing charge. Controlling the amount of charge on the floating gate alters the threshold voltage and creates a nonvolatile memory function. Flash memory development is therefore driven by some of the same concerns as MOS technology, but in addition to the demands for scalable devices with high access times and low leakage currents it adds to the requirement of efficient, controllable gate currents and channel hot electron (CHE) programming as used in conventional flash cells. However, as the drain and gate voltages are lowered the CHE programming becomes less efficient.
Another concern for both flash memories and MOSFET devices is the challenge of defining planar features, especially channel lengths at smaller dimensions. To overcome the limitations of determining the channel length by lithographic methods, vertical channel devices have been proposed in which the channel is formed on the sidewall of a trench, mesa or pillar. The length of the channel is then determined by epitaxial layer growth or etch rates in the devices.
Since flash memory is used mostly in mobile applications, low power operation is desirable. For programming with lower drain and gate voltages, a negative substrate voltage may be applied that produces a different programming mechanism that is more effective than the CHE programming at the lower voltages. Channel initiated secondary electron (CHISEL) injection occurs when a substrate bias is applied, and the mechanism is also known as substrate current induced hot electron (SCHE) injection. Channel electrons gain energy as they travel to the drain and produce primary impact ionization. The holes generated in the drain then travel back across the drain junction and gain energy as they pass through the depletion region where they can produce a secondary impact ionization (SII). The secondary electrons created by SII can travel back to the Si-SiO.sub.2 interface and be injected into the floating gate.
The present invention is directed to a flash memory cell and EEPROM device having a vertical channel and employing channel initiated secondary electron injection for programming.